Beneath-the-channel strain-transfer-structure (STS) and embedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs

We report the first demonstration of a novel transistor structure featuring a beneath-the-channel strain-transfer-structure (STS) and embedded source/drain (S/D) stressors for strain and performance enhancement. As compared to a transistor with standard S/D stressors, additional strain is imparted to the channel region by the STS due to coupling of its lattice interactions with the adjacent S/D stressors and the overlying channel region. Both strained n-FET with SiGe STS and silicon-carbon (SiC) S/D, and strained p-FET with SiC STS and SiGe S/D, were realized. The I performance of strained n- and p-FETs with STS and S/D stressors were enhanced by 42% and 60%, respectively, over unstrained control transistors for given DIBL of 0.15 V/V.