Overview of process integration issues for low K dielectrics

被引：22

作者：

Havemann, RH ^{[1
]}

Jain, MK ^{[1
]}

List, RS ^{[1
]}

Ralston, AR ^{[1
]}

Shih, WY ^{[1
]}

Jin, C ^{[1
]}

Chang, MC ^{[1
]}

Zielinski, EM ^{[1
]}

Dixit, GA ^{[1
]}

Singh, A ^{[1
]}

Russell, SW ^{[1
]}

Gaynor, JF ^{[1
]}

McKerrow, AJ ^{[1
]}

Lee, WW ^{[1
]}

机构：

[1] Texas Instruments Inc, Silicon Technol Dept, Dallas, TX 75265 USA

来源：

LOW-DIELECTRIC CONSTANT MATERIALS IV | 1998年 / 511卷

关键词：

D O I：

10.1557/PROC-511-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel tow k materials in multilevel interconnects.

引用

页码：3 / 14

页数：12