Enhanced surface preparation techniques for the Si/high-k interface

被引:7
作者
Barnett, J [1 ]
Young, CD [1 ]
Moumen, N [1 ]
Bersuker, G [1 ]
机构
[1] Int SEMATECH, Austin, TX 78741 USA
来源
ULTRA CLEAN PROCESSING OF SILICON SURFACES VII | 2005年 / 103-104卷
关键词
High-k; interfaces; charge trapping;
D O I
10.4028/www.scientific.net/SSP.103-104.11
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
引用
收藏
页码:11 / 14
页数:4
相关论文
共 3 条
[1]  
Bersuker G, 2004, MATER RES SOC SYMP P, V811, P31
[2]  
CHADWIN D, IN PRESS MICROELECTR
[3]   High-k gate stacks for planar, scaled CMOS integrated circuits [J].
Huff, HR ;
Hou, A ;
Lim, C ;
Kim, Y ;
Barnett, J ;
Bersuker, G ;
Brown, GA ;
Young, CD ;
Zeitzoff, PM ;
Gutt, J ;
Lysaght, P ;
Gardner, MI ;
Murto, RW .
MICROELECTRONIC ENGINEERING, 2003, 69 (2-4) :152-167