A fully synchronized, pipelined, and re-configurable 50Mb SRAM on 90nm CMOS technology for logic applications

被引：14

作者：

Zhang, K ^{[1
]}

Bhattacharya, U ^{[1
]}

Ma, L ^{[1
]}

Ng, Y ^{[1
]}

Zheng, B ^{[1
]}

Bohr, M ^{[1
]}

Thompson, S ^{[1
]}

机构：

[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年

关键词：

D O I：

10.1109/VLSIC.2003.1221219

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 50Mb SRAM chip is designed and fabricated on an industry leading 90nm CMOS technology that features a 1um(2) SRAM cell and 50nm gate length transistors with strained silicon[1]. The SRAM chip is formed with 100x512Kb subarrays that have 2.5 GHz nominal operating frequency, 75% area efficiency, and fully synchronized internal timing along with efficient local power-down feature. And the design can be easily re-configured to form large high-density on-die cache memory for high-speed logic applications such as CPUs.

引用

页码：253 / 254

页数：2