IBM PowerPC 440 FPU with complex-arithmetic extensions

The PowerPC((R)) 440 floating-point unit (FPU) with complex arithmetic extensions is an embedded application-specfic integrated circuit (ASIC) core designed to be used with the IBM PowerPC 440 processor core on the Blue Gene((R))/L compute chip. The FPU core implements the floating-point instruction set from the Power-PC Architecture (TM) and the floating-point instruction extensions created to aid in matrix and complex-arithmetic operations. The FPU instruction extensions define double-precision operations that are primarily; single-instruction multiple-data (SIMD) and require two (primary and secondary) arithmetic pipelines and floating-point register files. However, to aid complex-arithmetic routines, some FPU extensions actually perform (different (yet closely related) operations while executing in the arithmetic pipelines. The FPU core implements an operand crossbar between the primary and secondary arithmetic datapaths to enable each pipeline operand access from the primary or secondary register file. The Power PC 440 processor core provides 128-bit storage buses and simultaneous issue of an arithmetic instruction with a storage instruction, allowing the FPU core to fully utilize the parallel arithmetic pipes.