Gate dielectrics for ultimate CMOS technologies -: Limitations and alternative solutions

For nowadays CMOS technologies, the gate oxide thickness has reached a few nanometer range and will be lower than 2 nm for sub-0.1 mum generations. This scaling of the gate dielectric thickness favors the onset of physical phenomena such as gate polysilicon depletion or quantum effects that limit the MOS device performance in terms of capacitance and leakage current. Moreover, these ultra thin oxide MOS structures are prone to new degradation processes that could reduce their operation lifetime. In this paper, the major limitations raised by the scaling of the gate dielectrics in CMOS technologies are briefly reviewed in terms of MOS capacitance, reliability and new materials issues. More specifically, we first focus on the limitations raised by physical phenomena inherent to MOS capacitors such as polysilicon depletion and quantum effects (carrier confinement and tunneling), impacting their performances. We then address the limitations related to the reliability concerns such as wearout, breakdown, quasi-breakdown, stress-induced leakage current, determining the device lifetime. Finally, the new materials currently envisaged, as replacement solutions in order to overcoming the difficulties due to the gate oxide scaling will be discussed. Tn particular, the possible solutions based on alternate high permittivity gate dielectrics and metallic gate materials will be emphasized. (C) 2000 Academie des sciences/Editions scientifiques et medicales Elsevier SAS.