Lateral smart-discrete process and devices based on thin-layer silicon-on-insulator

被引：29

作者：

Letavic, T ^{[1
]}

Petruzzello, J ^{[1
]}

Simpson, M ^{[1
]}

Curcio, J ^{[1
]}

Mukherjee, S ^{[1
]}

Davidson, J ^{[1
]}

Peake, S ^{[1
]}

Rogers, C ^{[1
]}

Rutter, P ^{[1
]}

Warwick, M ^{[1
]}

Grover, R ^{[1
]}

机构：

[1] Philips Res USA, Briarcliff Manor, NY 10510 USA

来源：

ISPSD'01: PROCEEDINGS OF THE 13TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS | 2001年

关键词：

D O I：

10.1109/ISPSD.2001.934640

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A ten-mask lateral smart-discrete process technology which combines novel high-voltage RESURF transistor structures and a merged bipolar/DMOS process flow on thin-layer SOI substrates is presented. Benchmarking shows that 650V/1.2 Ohm SOI lateral smart-discrete devices exhibit a total gate charge which is a factor-of-two lower than vertical super-junction devices, a temperature-independent body diode reverse recovery time which is a factor-of-two smaller than vertical ultrafast silicon diodes, and total hard-switching losses which are lower than conventional VDMOS. The total gate charge, reverse recovery time, and switching delay times are the lowest reported values for 650V silicon devices. This, in conjunction with a process with integrated logic, establishes SOI smart-discrete technology as best-in-class for efficient high-frequency power conversion.

引用

页码：407 / 410

页数：4

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IEE REVIEW, 2000, 46 (06) :23-27

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