Minimizing linewidth roughness in Step and Flash Imprint Lithography

被引:5
作者
Khusnatdinov, Niyaz [1 ]
Schmid, Gerard M. [1 ]
Brooks, Cynthia B. [1 ]
LaBrake, Dwayne [1 ]
Resnick, Douglas J. [1 ]
Hart, Mark W. [2 ]
Gopalakrishnan, Kailash [2 ]
Shenoy, Rohit [2 ]
Jih, Ron [2 ]
Zhang, Ying [3 ]
Sikorski, Edmund [3 ]
Rothwell, Mary Beth [3 ]
Owens, Jordan [4 ]
Ford, Arnie [4 ]
机构
[1] Mol Imprints Inc, Austin, TX 78758 USA
[2] IBM Corp, Almaden Res Ctr, San Jose, CA 95120 USA
[3] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[4] Sematech ATDF, Austin, TX 78741 USA
关键词
S-FIL; template; imprint lithography; replication; linewidth roughness;
D O I
10.1016/j.mee.2008.01.041
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Optical lithography has been successful in achieving deep sub-wavelength images by the continuous improvement of lens systems, resists and the introduction of phase shift masks. One of the key challenges in attempting to pattern feature sizes less than 32 nm is the ability to minimize feature roughness while maintaining acceptable process throughput. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Step and Flash Imprint Lithography is a step-and-repeat imprint process that has demonstrated excellent feature resolution. Since the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. In this paper, LWR was evaluated for several different templates. Feature sizes ranging from 20 nm to 50 nm were studied, and LWR was calculated from SEM images of the template, on imprinted wafers, and after pattern transfer. On average, LWR was extremely low (less than 3 nm, 3 sigma), and independent of the processing step and feature size. A minimum LWR of 1.7 nm was achieved, which is the required LWR for processing at the 32 nm node. (c) 2008 Elsevier B.V. All rights reserved.
引用
收藏
页码:856 / 860
页数:5
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