Optimal fault detection for analogue circuits under manufacturing tolerances

被引：1

作者：

Gielen, G ^{[1
]}

Wang, Z ^{[1
]}

Sansen, W ^{[1
]}

机构：

[1] NATL FUND SCI RES,BRUSSELS,BELGIUM

来源：

ELECTRONICS LETTERS | 1996年 / 32卷 / 01期

关键词：

fault location; analogue circuits; integrated circuits;

D O I：

10.1049/el:19960056

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An optimal method for analogue fault detection is presented. Instead of using arbitrary decision windows, the method fully considers the VLSI manufacturing tolerances and mismatches to minimise the probability of erroneous test decision. A-priori simulated probability information is combined with the actual measurement data to decide whether the circuit is fault-free or faulty. Experimental results show the effectiveness of the proposed technique.

引用

页码：33 / 34

页数：2