Partial silicides technology for tunable work function electrodes on high-k gate dielectrics -: Fermi level pinning controlled PtSix for HfOx(N) pMOSFET

被引：42

作者：

Nabatame, T ^{[1
]}

Kadoshima, M ^{[1
]}

Iwamoto, K ^{[1
]}

Mise, N ^{[1
]}

Migita, S ^{[1
]}

Ohno, M ^{[1
]}

Ota, H ^{[1
]}

Yasuda, N ^{[1
]}

Ogawa, A ^{[1
]}

Tominaga, K ^{[1
]}

Satake, H ^{[1
]}

Toriumi, A ^{[1
]}

机构：

[1] MIRAI, ASET, Tsukuba, Ibaraki 3058569, Japan

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419072

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We investigate an origin of the Fermi-level pinning at the gate electrode/HfOx(N) interface, and propose a new technology for tuning the work function with a partial silicidation of Pt on HfOx(N). It is clearly shown that the effective work functions (phi(m,eff)) of fully silicided (FUSI) NiSi and PtSi on HfOx(N) are rigidly fixed due to the Fermi-level pinning, and that the impurity doping does not help changing phi(m,eff) at all. The large flatband voltage (V-FB) shifts of FUSI PtSi MOSFETs have been observed irrespective of Si deposition processes. On the basis of these new findings, nMOSFET with pinned n(+)poly-Si and pMOSFET with partially pinned PtSi on HfOx(N) for a balanced CMOS have been proposed, and both of them have shown good electrical properties. Furthermore, it is experimentally discussed that the control of the Si atom content at the PtSix/HfO2 interface is a key factor to relax the pinning effect. The partial silicidation technology will be a most feasible method for advanced metal gate CMOS.

引用

页码：83 / 86

页数：4

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