An 8-GHz, continuous-time Σ-Δ analog-digital converter in an InP-based HBT technology

被引：14

作者：

Krishnan, S ^{[1
]}

Scott, D ^{[1
]}

Griffith, Z ^{[1
]}

Urteaga, M ^{[1
]}

Parthasarathy, N ^{[1
]}

Rodwell, M ^{[1
]}

机构：

[1] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA

来源：

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2003年 / 51卷 / 12期

关键词：

analog-to-digital converter (ADC); continuous time; delta-sigma; HBTs; InP;

D O I：

10.1109/TMTT.2003.820176

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report an 8-GHz clock-rate, second-order continuous-time Sigma-Delta analog-digital converter (ADC) that achieves 57.4-, 51.7-, and 40.2-dB SNR at signal sampling rates of 125, 250, and 500 Ms/s, respectively. The integrated circuit occupied 1.45-mm(2) die area, contains 76 transistors, is fabricated in an InP-based HBT technology, and dissipates similar to 1.8 W. We also study the effect of excess delay on modulator performance, and show that excess delay does not affect performance as long as the centroid-in-time of the digital-analog converter pulse remains stationary.

引用

页码：2555 / 2561

页数：7

共 15 条

[1]

CANDY JC, 1992, OVERSAMPLING DELTA S, P1

[2] PRECISION DIFFERENTIAL VOLTAGE-CURRENT CONVERTER [J].

CAPRIO, R .

ELECTRONICS LETTERS, 1973, 9 (06) :147-148

[3]

CHAN KT, 1992, 1992 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, P1300, DOI 10.1109/ISCAS.1992.230266

[4] Excess loop delay in continuous-time delta-sigma modulators [J].

Cherry, JA ;

Snelgrove, WM .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1999, 46 (04) :376-389

[5]

COMINO V, 1991, IEEE J SOLID-ST CIRC, V26, P176, DOI 10.1109/4.74994

[6]

DAHLSTROM M, 2003, DEV RES C LAT NEWS S, P23

[7]

Harrison J, 2000, ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL III, P746, DOI 10.1109/ISCAS.2000.856168

[8]

HORBACH U, 1990, INT CIRC SYST S NEW, P2789

[9] An 18-GHz continuous-time Σ-Δ analog-digital converter implemented in InP-transferred substrate HBT technology [J].

Jaganathan, S ;

Krishnan, S ;

Mensa, D ;

Mathew, T ;

Betser, Y ;

Wei, Y ;

Scott, D ;

Urteaga, M ;

Rodwell, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (09) :1343-1350

[10] A 3.2-GHZ 2ND-ORDER DELTA-SIGMA MODULATOR IMPLEMENTED IN INP HBT TECHNOLOGY [J].

JENSEN, JF ;

RAGHAVAN, G ;

COSAND, AE ;

WALDEN, RH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (10) :1119-1127

← 1 2 →