Multi-valued logic synthesis

被引：28

作者：

Brayton, RK ^{[1
]}

Khatri, SP ^{[1
]}

机构：

[1] Univ Calif Berkeley, Berkeley, CA 94720 USA

来源：

TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/ICVD.1999.745148

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 [计算机科学与技术];

摘要：

We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.

引用

页码：196 / 205

页数：10

共 10 条

[1]

BRAYTON RK, 1997, INT WORKSH LOG SYNTH

[2]

BRZOZOWSKI JA, 1997, P INT WORKSH FORM LA

[3]

IYER M, 1996, P 33 DES AUT C

[4]

KHATRI S, 1999, IN PRESS P INT C VLS

[5]

LAVAGNO L, 1990, P INT C COMP AID DES

[6]

MALIK S, 1990, P INT C COMP AID DES

[7]

MEHROTRA A, 1997, P INT C COMP AID DES

[8]

MICHELI GD, 1984, P INT C COMP AID DES

[9]

NOVA - STATE ASSIGNMENT OF FINITE STATE MACHINES FOR OPTIMAL 2-LEVEL LOGIC IMPLEMENTATION [J].

VILLA, T ;

SANGIOVANNIVINCENTELLI, A .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1990, 9 (09) :905-924

[10]

YAMASHITA S, 1996, P INT C COMP AID DES

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