Multi-valued logic synthesis

被引:28
作者
Brayton, RK [1 ]
Khatri, SP [1 ]
机构
[1] Univ Calif Berkeley, Berkeley, CA 94720 USA
来源
TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1999年
关键词
D O I
10.1109/ICVD.1999.745148
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 [计算机科学与技术];
摘要
We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.
引用
收藏
页码:196 / 205
页数:10
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