Evaluation of phase-edge phase-shifting mask for sub-0.18μm gate patterns in logic devices

被引：11

作者：

Cha, DH ^{[1
]}

Kye, JW ^{[1
]}

Seong, NG ^{[1
]}

Kang, HY ^{[1
]}

Cho, HK ^{[1
]}

Moon, JT ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Semicond R&D Ctr, Kyungki Do 449900, South Korea

来源：

OPTICAL MICROLITHOGRAPHY XI | 1998年 / 3334卷

关键词：

phase shifting mask; PSM; CD control; logic device; phase-edge; lithography;

D O I：

10.1117/12.310780

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The speed of logic device is mainly dependent on gate length. To achieve process margin (DOF, E/T, etc.) and minimize On Chip Variation (OCV) of logic gate with sub 0.18mm design rule, the need for phase-edge PSM technology that has the advantages of minimum resolution and Critical Dimension (CD) control has been increased. In this paper, performance and feasibility of phase-edge PSM technology were investigated. Using phase-edge PSM and positive resist process at DUV wavelength (lambda=248nm), the possibility of 0.10 mu m logic gate patterning was confirmed and 0.18 mu m gate lines with DOF larger than 1.0 mu m and +/-6% CD variation were obtained. And design rules for phase-edge layout generation were extracted. Then the possibility of layout generation by the extracted design rules and layout conversion tool was confirmed. Also, the feasibility of mask CD uniformity and phase uniformity, and alignment between phase-edge mask and normal chrome (Cr) mask was investigated and confirmed. Considering lithographic performance and process feasibility, phase-edge PSM technology is a very promising method for patterning sub 0.18 mu m gate in logic devices.

引用

页码：46 / 54

页数：3