InterChip Via technology for Vertical System Integration

被引：57

作者：

Ramm, P ^{[1
]}

Bonfert, D ^{[1
]}

Gieser, H ^{[1
]}

Haufe, J ^{[1
]}

Iberl, F ^{[1
]}

Klumpp, A ^{[1
]}

Kux, A ^{[1
]}

Wieland, R ^{[1
]}

机构：

[1] Fraunhofer Inst Reliabil & Microintegrat, Munich, Germany

来源：

PROCEEDINGS OF THE IEEE 2001 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2001年

关键词：

D O I：

10.1109/IITC.2001.930046

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Vertical System Integration VSI (R) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested device substrates (see Figure 1). The InterChip Via (ICV) technology is introduced and discussed as a fully CMOS-compatible wafer-scale process which provides vertical electrical interchip interconnects placed at arbitrary locations, without intervention to the IC's fabrication technologies. Thinning of the device substrate (150 mm) down to 10 mum as well as bonding it to an other silicon wafer had basically no influence on the electrical performance of EEPROM-products and process monitor structures. Resistances of 2 Omega for a 2 x 2 C mu (2) interchip via contact and working contact chains with 480 interchip via contacts are promising results for the future fabrication of multi-layered three-dimensional systems combining the advantages of different device technologies.

引用

页码：160 / 162

页数：3

共 2 条

[1] Three dimensional metallization for vertically integrated circuits (invited lecture) [J].

Ramm, P ;

Bollmann, D ;

Braun, R ;

Buchner, R ;

Cao-Minh, U ;

Engelhardt, M ;

Errmann, G ;

Grassl, T ;

Hieber, K ;

Hubner, H ;

Kawala, G ;

Kleiner, M ;

Klumpp, A ;

Kuhn, S ;

Landesberger, C ;

Lezec, H ;

Muth, M ;

Pamler, W ;

Popp, R ;

Renner, E ;

Ruhl, G ;

Sanger, A ;

Scheler, U ;

Schertel, A ;

Schmidt, C ;

Schwarzl, S ;

Weber, J ;

Weber, W .

MICROELECTRONIC ENGINEERING, 1997, 37-8 (1-4) :39-47

[2]

RAMM P, Patent No. 5766984

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