Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs

被引：14

作者：

Zhang, H ^{[1
]}

Wan, M ^{[1
]}

George, V ^{[1
]}

Rabaey, J ^{[1
]}

机构：

[1] Univ Calif Berkeley, Berkeley, CA 94720 USA

来源：

IEEE COMPUTER SOCIETY WORKSHOP ON VLSI '99, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/IWV.1999.760456

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present and analyze a number of interconnect architectures for reconfigurable systems targeting applications in the areas of wireless communication and multimedia processing. Several interconnect architectures suitable for heterogeneous elements are proposed and then a methodology to evaluate the architectures is described. The results indicate that the hierarchical generalized mesh structure shows the most promise in terms of energy efficiency, as it can optimize both local and global connections.

引用

页码：2 / 8

页数：7