A vertex trigger based on cylindrical multiwire proportional chambers

被引:30
作者
Becker, J. [1 ]
Boesiger, K. [1 ]
Lindfeld, L. [1 ]
Mueller, K. [1 ]
Robmann, P. [1 ]
Schmitt, S. [1 ]
Schmitz, C. [1 ]
Steiner, S. [1 ]
Straumann, U. [1 ]
Szeker, K. [1 ]
Truoel, P. [1 ]
Urban, M. [1 ]
Vollhardt, A. [1 ]
Werner, N. [1 ]
Baumeister, D. [2 ]
Loechner, S. [2 ]
Hildebrandt, M. [3 ]
机构
[1] Univ Zurich, Inst Phys, CH-8057 Zurich, Switzerland
[2] Kirchhoff Inst Phys, ASIC Lab, D-69120 Heidelberg, Germany
[3] Paul Scherrer Inst, CH-5232 Villigen, Switzerland
关键词
FPGA; ASIC; MWPC; trigger; H1; HERA;
D O I
10.1016/j.nima.2007.11.024
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
This article describes the technical implementation and the performance of the z-vertex trigger (CIP2k), which is part of the H1-experiment at HERA. The HERA storage ring and collider was designed to investigate electron (and positron) proton scattering at a center-of-mass energy of 320 GeV. To improve the sensitivity for detecting non-standard model physics and other high momentum transfer phenomena, the HERA ring has been ungraded between 2000 and 2003 to increase the specific luminosity for the experiments. In order to cope with the increased event and background rate the experiments were upgraded, too. The CIP2k trigger system is based on a set of five cylindrical multiwire proportional chambers with cathode pad readout, and allows to distinguish between events induced by beam background and ep-interactions at the first trigger stage. The trigger decision is calculated dead-time free with a latency of 1.5 mu s in parallel to the beam clock at 10.4 MHz. The trigger-logic is realized in large field programmable gate arrays (FPGA) using the hardware description language Verilog. The system is operational since October 2003. It suppresses background events with high efficiency and provides event timing information, as designed. (C) 2007 Elsevier B.V. All rights reserved.
引用
收藏
页码:190 / 203
页数:14
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