A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-mu m CMOS

被引:138
作者
Craninckx, J
Steyaert, MSJ
机构
[1] Departement Elektrotechniek, Afd. ESAT-MICAS, Katholieke Universiteit Leuven
[2] Katholieke Universiteit Leuven, Heverlee
[3] University of California, Los Angeles, CA
关键词
D O I
10.1109/4.508200
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-mu m CMOS technology, A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained, The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage, Running at a power supply of 3 V, the circuit consumes 8 mA at a maximum input frequency of 1.75 GHz.
引用
收藏
页码:890 / 897
页数:8
相关论文
共 7 条
[1]   A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler [J].
Craninckx, J ;
Steyaert, MSJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (12) :1474-1482
[2]   Low-noise voltage-controlled oscillators using enhanced LC-tanks [J].
Craninckx, J ;
Steyaert, M .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (12) :794-804
[3]  
CROLS J, 1995, ISSCC, P136
[4]   CMOS HIGH-SPEED DUAL-MODULUS FREQUENCY-DIVIDER FOR RF FREQUENCY-SYNTHESIS [J].
FOROUDI, N ;
KWASNIEWSKI, TA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (02) :93-100
[5]  
MIN J, 1994, PROCEEDINGS OF THE IEEE 1994 CUSTOM INTEGRATED CIRCUITS CONFERENCE, P379, DOI 10.1109/CICC.1994.379698
[6]  
ROGENMOSER R, 1993, P IEEE 1993 CUST INT
[7]  
ROGENMOSER R, 1994, P IEEE 1994 CUST INT