Ultrashallow junction formation for sub-100 nm complementary metal-oxide-semiconductor field-effect transistor by controlling transient enhanced diffusion

The annealing process of implantation damage that induces transient enhanced diffusion during a subsequent thermal process such as low-pressure chemical vapor deposition (LPCVD) is optimized from the viewpoint of the process integration of an 80 run physical gate length complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) device. For nMOSFETs, a temperature as high as 960 degreesC is necessary to prevent transient enhanced diffusion. In contrast, for pMOSFETs, higher temperature annealing promotes thermal diffusion instead of preventing enhanced diffusion. It is found that a separate annealing process sequence is required. In utilizing preamorphization implantation prior to boron implantation, however, higher temperature annealing is effective for forming an ultrashallow junction. Consequently, the annealing processes can be performed simultaneously.