Compact SPICE modeling and design optimization of low leakage a-Si:H TFTs for large-area imaging systems

We present a SPICE model that takes into account the different mechanisms contributing to leakage current in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The main sources of leakage current in these devices have been identified to be the parasitic reverse-biased p-i-n diode at the vicinity of the drain as well as diffusion of phosphorous atoms from micro-crystalline (n(+)mu c-Si:H) contact layer into the intrinsic a-Si:H region. The latter gives rise to ohmic conduction which dominates at very low drain voltages (< 1 V) and very low gate voltages (< 5 V). At higher gate voltages (5V less than or equal to V-G less than or equal to 20 V), the reverse current of the parasitic p-i-n diode can be attributed to thermal generation of electrons from the valence to conduction bands through the mid-gap states in the a-Si:H. At even higher gate voltages (> 20 V), the reverse current is due to trap-assisted tunneling, whereby the electrons tunnel to the conduction band via the mid-gap states. A systematic characterization of TFTs with different a-Si:H layer thicknesses shows that the optimal thickness for low leakage current is around 50 nm. The bias dependent leakage current behavior has been modeled and implemented in SPICE using simple circuit elements based on voltage controlled current sources (VCCS). Simulated and measured reverse leakage current characteristics are in reasonable agreement.