Improvement of electrical yield in the fabrication of CIGS-based thin-film modules

Gradually moving toward the micro (or primitive) pilot-production stage from the R&D stage, an attempt to improve yield as well as efficiency on 30 x 30-cm-sized CIGS-based circuits is carried out. Applying the LBIC mapping technique to the analysis of CIGS-based circuits, the CIGS-based absorber formation and Zn(O,S,OH)(x) buffer deposition stages in the baseline process are mainly adjusted and revised. Through trouble shooting on the current baseline process, the champion efficiency is improved from 11.6 to 12.5% and the electrical yield of CIGS-based circuits over 10% efficiency is enhanced from 7 to 50%. Based upon the analysis of the results from the relatively large volume of CIGS-based circuits, it is recognized that reducing unnoticed or unexpected factors in the fabrication process for CIGS-based circuits is important to make the baseline process more robust and reproducible. (C) 2001 Elsevier Science B.V. All rights reserved.