A low power, transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI)

被引：14

作者：

Austin, BL ^{[1
]}

Bowman, KA ^{[1
]}

Tang, XH ^{[1
]}

Meindl, JD ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

ELEVENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/ASIC.1998.722816

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new compact transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced. The model, verified against MEDICI and HSPICE, describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of 1)carrier velocity saturation, 2)vertical and lateral high field mobility degradation, and 3)threshold voltage roll-off all prominent characteristics of submicron devices. The key contribution of this model as the physical insight into the on/off current tradeoff that ensues with voltage scaling and will be vital to future low power design. Utilizing the model for a complete power-delay analysis of CMOS circuit designs, analytical expressions are derived for: 1)propagation delay, 2)short circuit power (P-SC), and 3)static power (P-Static). Results from the total power (P-Total) consumption analysis indicate that P-SC and P-Static may constitute over 1/3 of P-Total in future low power/high performance CMOS GSI.

引用

页码：125 / 129

页数：5