Focal-plane analog VLSI cellular implementation of the boundary contour system

被引:8
作者
Cauwenberghs, G [1 ]
Waskiewicz, J [1 ]
机构
[1] Johns Hopkins Univ, Dept Elect & Comp Engn, Baltimore, MD 21218 USA
关键词
active pixel sensors; analog VLSI; boundary segmentation; cellular neural networks (CNN's); focal-plane image processing; neuromorphic engineering;
D O I
10.1109/81.747215
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present an analog very large scale integration (VLSI) cellular architecture implementing a version of the boundary contour system (BCS) for real-time focal-plane image processing. Inspired by neuromorphic models across the retina and several layers of visual cortex, the design integrates in each pixel the functions of phototransduction and simple cells, complex cells, hypercomplex cells, and bipole cells in each of three directions interconnected on a hexagonal grid. Analog current-mode complementary metal-oxide-semiconductor (CMOS) circuits are used throughout to perform edge detection, local inhibition, directionally selective long-range diffusive kernels, and renormalizing global gain control, Experimental results from a fabricated 12 x 10 pixel prototype in a 1.2-mu m CMOS process are included, demonstrating the robustness of the implemented BCS model in selecting image contours in a cluttered and noisy background.
引用
收藏
页码:327 / 334
页数:8
相关论文
共 15 条
[11]   A neural model of contour integration in the primary visual cortex [J].
Li, ZP .
NEURAL COMPUTATION, 1998, 10 (04) :903-940
[12]   A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm [J].
McIlrath, LD .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (09) :1239-1247
[13]  
MIYAKE Y, 1996, P IEEE LAS EL C LEOS
[14]   THE CNN UNIVERSAL MACHINE - AN ANALOGIC ARRAY COMPUTER [J].
ROSKA, T ;
CHUA, LO .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1993, 40 (03) :163-173
[15]   An integrated cortical layer for orientation enhancement [J].
Venier, P ;
Mortara, A ;
Arreguit, X ;
Vittoz, EA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (02) :177-186