3D chip stack technology using through-chip interconnects

被引：53

作者：

Benkart, P

Heittmann, A

Huebner, H

Ramacher, U

Kaiser, A

Munding, A

Bschorr, M

Pfleiderer, HJ

Kohn, E

机构：

[1] Univ Ulm, Dept Elect Devices & Circuits, Ulm, Germany

[2] Univ Ulm, Dept Microelect, Ulm, Germany

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2005年 / 22卷 / 06期

关键词：

D O I：

10.1109/MDT.2005.125

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A key enable for 3D technologies is the ability to stack chips and build interconnects that connect circuitry in different layers of the stack. This article presents a technology overview of how to achieve this goal in a 3D fabrication process. It also shows measurements for characterizing these interconnects. © 2005 IEEE.

引用

页码：512 / 518

页数：7

共 13 条

[1] A review of 3-D packaging technology [J].

Al-Sarawi, SF ;

Abbott, D ;

Franzon, PD .

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1998, 21 (01) :2-14

[2]

[Anonymous], 2004, P 2004 INT S PHYS DE

[3] Stackable system-on-packages with integrated components [J].

Becker, KF ;

Jung, E ;

Ostmann, A ;

Braun, T ;

Neumann, A ;

Aschenbrenner, R ;

Reichl, H .

IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2004, 27 (02) :268-277

[4] A Test- and Drive Circuit for a novel 3D Connection Technology [J].

Bschorr, M. ;

Pfleiderer, H-J ;

Benkart, P. ;

Kaiser, A. ;

Munding, A. ;

Kohn, E. ;

Heittmann, A. ;

Huebner, H. ;

Ramacher, U. .

ADVANCES IN RADIO SCIENCE, 2005, 3 :305-310

[5] Advanced processing techniques for through-wafer interconnects [J].

Burkett, SL ;

Qiao, X ;

Temple, D ;

Stoner, B ;

McGuire, G .

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2004, 22 (01) :248-256

[6]

HEUBERGER A, 1991, MIKROMECHANIK, P145

[7]

HUEBNER H, 2002, P ADV MET C AMC 02 M, P53

[8] 3D stackable packages with bumpless interconnect technology [J].

Lin, CWC ;

Chiang, SCL ;

Yang, TKA .

PROCEEDINGS OF 5TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2003, :8-12

[9] 4-STORY STRUCTURED CHARACTER-RECOGNITION SENSOR IMAGE WITH 3D INTEGRATION [J].

OHTAKE, K ;

KIOI, K ;

SHINOZAKI, T ;

TOYOYAMA, S ;

SHIRAKAWA, K ;

TSUCHIMOTO, S .

MICROELECTRONIC ENGINEERING, 1991, 15 (1-4) :179-182

[10] High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging [J].

Ok, SJ ;

Kim, CH ;

Baldwin, DF .

IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2003, 26 (03) :302-309

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