Stencil printing process development for low cost flip chip interconnect

Traditional methods for forming flip chip interconnection include evaporation and electroplating. While both options have proven performance records, their costs are too high for many of today's cost-sensitive applications. Motorola AISL (Advanced Interconnect Systems Laboratory) developed a low cost flip chip interconnect alternative, which electroless plates Ni/Au as the under bump metallurgy (UBM), deposits solder paste using a stencil or photoresist mask, and renews the paste to form solder bumps. This paper is focused on the stencil print process development for wafer solder bumping. Solder paste selection, characterization, stencil design, and process parameter optimization are critical factors for successful fine pitch stencil printing. Fine mesh eutectic solder pastes (Type 5: -500+635, Type 6: -635) with different flux vehicles were evaluated for printability and reflow studies. Paste and flux modification and co-development with vendors for this specific application were conducted. An optimal paste, with specified viscosity and desired print, renew and cleaning behavior, was developed. Wafer stencil design rules were established to deposit the right amount of solder paste to form the required reflowed solder bump height without bridges between pads. Printing and reflow design of experiments were performed to establish the baseline and optimum process parameters. Solder bump characterizations, including bump height and uniformity, composition, shear force, and SEM bump profile and crossection microstructure analysis, were conducted. Development and characterization results are presented. This stencil print solder bump process is demonstrated on 4, 5, 6, and 8 in. device wafers with pitch down to 200 mu m. Solder bumps are formed on wafers without bridges or missing bumps. Bump height standard deviation within die is less than 3.5 mu m, and range is less than 20 mu m. The 63Sn/37Pb eutectic-bumped functional device dice were flip chip assembled to test boards with Cu/Ni/Au pad metallization, and underfilled for interconnect reliability study. All reliability requirements were met. Reliability and failure analysis results are presented.