Power-aware scheduling under timing constraints for mission-critical embedded systems

被引:42
作者
Liu, JF [1 ]
Chou, PH [1 ]
Bagherzadeh, N [1 ]
Kurdahi, F [1 ]
机构
[1] Univ Calif Irvine, Dept Elect & Comp Engn, Irvine, CA 92697 USA
来源
38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001 | 2001年
关键词
D O I
10.1109/DAC.2001.935622
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget is low, but also deliver high performance when required. This paper presents a new scheduling technique for supporting the, design and evaluation of a class of power-aware systems in mission-critical applications. It satisfies stringent min/max timing and max power constraints. It also makes the best effort to satisfy the min power constraint in an attempt to fully utilize free power or to control power jitter. Experimental results show that our scheduler can improve performance and reduce energy cost simultaneously compared to hand-crafted designs for previous missions. This tool forms the basis of the IM-PACCT system-level framework that will enable designers to explore many power-performance, trade-offs with confidence.
引用
收藏
页码:840 / 845
页数:6
相关论文
共 7 条
[1]  
CHOU P, 1995, P ACM IEEE DAC, P462
[2]  
CHOU P, 1994, P DES AUT C, P1
[3]  
CHUNG EY, 1999, P INT C COMP AID DES, P274
[4]  
LIU JF, 2001, IMPACCT010301 U CAL
[5]  
Okuma T., 1999, Proceedings 12th International Symposium on System Synthesis, P24, DOI 10.1109/ISSS.1999.814256
[6]  
Simunic T., 1999, Proceedings 12th International Symposium on System Synthesis, P18, DOI 10.1109/ISSS.1999.814255
[7]   Predictive system shutdown and other architectural techniques for energy efficient programmable computation [J].
Srivastava, MB ;
Chandrakasan, AP ;
Brodersen, RW .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1996, 4 (01) :42-55