Accelerating colour space conversion on reconfigurable hardware

被引：18

作者：

Bensaali, F ^{[1
]}

Amira, A ^{[1
]}

机构：

[1] Queens Univ Belfast, Sch Comp Sci, Belfast BT7 1NN, Antrim, North Ireland

来源：

IMAGE AND VISION COMPUTING | 2005年 / 23卷 / 11期

关键词：

colour space conversion; field programmable gate array; distributed arithmetic;

D O I：

10.1016/j.imavis.2005.03.006

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Colour space conversion is very important in many types of image processing applications including video compression. This operation consumes up to 40% of the entire processing power of a highly optimised decoder. Therefore, techniques which efficiently implement this conversion are desired. This paper presents two novel architectures for efficient implementation of a Colour Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000 FPGA development board. In addition, they are platform independent and have a low latency (eight cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/s. (c) 2005 Elsevier B.V. All rights reserved.

引用

页码：935 / 942

页数：8

共 19 条

[1]

Albiol A, 2001, 2001 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL II, PROCEEDINGS, P681, DOI 10.1109/ICIP.2001.958585

[2]

*ALMA TECHN, 2002, HIGH PERF COL SPAC C

[3]

AMIRA A, 2001, THESIS QUEENS U BELF

[4]

AMIRA A, 2003, P INT C IM PROC ICIP

[5]

*AMPH SEM LTD, 2002, COL SPAC CONV

[6]

BARTKOWIAK M, 2001, EURASIP ECMCS 2001 B

[7]

BENSAALI F, 2003, INT C COMP COMM CONT

[8]

BENSAALI F, 2004, LECT NOTES COMPUTER

[9]

BENSAALI F, 2003, 10 IEEE INT C EL CIR

[10]

BRACAMONTE J, 2000, IEEE NORD SIGN PROC

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