An all adder systolic structure for fast computation of moments

被引:32
作者
Chan, FHY [1 ]
Lam, FK [1 ]
Li, HF [1 ]
Liu, JG [1 ]
机构
[1] CONCORDIA UNIV,DEPT COMP SCI,MONTREAL,PQ H3G 1M8,CANADA
来源
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 1996年 / 12卷 / 02期
关键词
D O I
10.1007/BF00924524
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Moment invariants play an important role in pattern recognition and computer vision. They have the nice properties of being invariant under translation, rotation and scaling. In this paper, we propose a new systolic array for computing ordinary moments from which moment invariants can be derived. The array exploits parallelism of the computation maximally and has an ideal time complexity of O(n). Each computation step involves a single addition only and is thus far superior to most existing solutions that require multiplication. The systolic array can be directly implemented in VLSI and we also provide an estimate-of the realizability of the array in a 0.8 micron BiCMOS technology. To achieve effective tradeoff between area and time requirement, we also propose a scalable array that allows us to fold the computation into a much smaller area. Our solution is suitable for both binary images and gray level images and is thus superior to an earlier work that has similar characteristics.
引用
收藏
页码:159 / 175
页数:17
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