Design, implementation and analysis of a new redundant CORDIC processor with constant scaling factor and regular structure

A new high-speed redundant CORDIC processor is designed and implemented based on the double rotation method, which turns out to be the two-dimensional (2D) Householder CORDIC, a special case of the generalized Householder CORDIC in the 2D Euclidean Vector space. The new processor has the advantages of regular structure and high throughput rate. The pipelined structure with radix-2 signed-digit (SD) redundant arithmetic is adopted to reduce the carry-propagation delay of the adders while the digit-serial structure alleviates the burden of the hardware cost and I/O requirement. Compared to previously proposed designs, the new CORDIC processor preserves the constant scaling factor, an important merit of the original CORDIC, and thus does not require any complicated division or square-root operations for variable scaling factor calculation. Furthermore, the processor is well suited to VLSI implementation since it does not call for any irregularly inserted correcting iterations. Both angle calculation mode for computing trigonometric function and vector rotation mode for plane rotations are supported. Practical VLSI chip implementation of the fixed-point redundant CORDIC processor using 0.6 mu m standard cell library is given including detailed numerical error analysis.