Leading-one Prediction scheme for latency improvement in single datapath floating-point adders
被引:10
作者:
Bruguera, JD
论文数: 0引用数: 0
h-index: 0
机构:
Univ Santiago de Compostela, Dept Elect & Comp Engn, Santiago De Compostela 15706, SpainUniv Santiago de Compostela, Dept Elect & Comp Engn, Santiago De Compostela 15706, Spain
Bruguera, JD
[1
]
Lang, T
论文数: 0引用数: 0
h-index: 0
机构:
Univ Santiago de Compostela, Dept Elect & Comp Engn, Santiago De Compostela 15706, SpainUniv Santiago de Compostela, Dept Elect & Comp Engn, Santiago De Compostela 15706, Spain
Lang, T
[1
]
机构:
[1] Univ Santiago de Compostela, Dept Elect & Comp Engn, Santiago De Compostela 15706, Spain
来源:
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS
|
1998年
关键词:
D O I:
10.1109/ICCD.1998.727065
中图分类号:
TP3 [计算技术、计算机技术];
学科分类号:
0812 ;
摘要:
This paper describes the design of a Leading-one Predictor (LOP) for floating-point addition, with an exact determination of the shift amount required. Previous LOP proposals produce a shift amount which might be in error by one position, so that this error has to be corrected after the addition terminates, increasing the critical path. Our design incorporates a concurrent detection of this error so that the amount of shift is corrected before the actual shift, without increasing the latency. The scheme presented here is applicable to the common case of a single datapath floating-point addition in which the output of the adder is always positive. We estimate the reduction in the critical path and the increase in area.