Reduce beat and harmonics in grid-connected three-level voltage-source converters with low switching frequencies

被引:10
作者
Wang, Fred [1 ]
机构
[1] Virginia Polytech Inst & State Univ, Ctr Power Elect Syst, Bradley Dept Elect & Comp Engn, Blacksburg, VA 24061 USA
基金
欧洲研究理事会; 美国国家科学基金会;
关键词
beat; neutral-point-clamped (NPC) converter; three-level converter;
D O I
10.1109/TIA.2007.904434
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper investigates low-frequency beat and harmonics in grid-connected three-level pulsewidth-modulated (PWM) voltage-source converters with low switching frequencies. The impact of switching frequencies and switching sequence, as well as mitigation techniques, are studied. Different from some recent results, the analysis confirms the advantages of selecting switching frequency, as an odd-triplen multiple of the grid operating frequency, for eliminating imbalance and undesirable even-order harmonics, which can negatively impact the dc-link neutral-point balance in a three-level converter. Tests and analysis show that low-frequency subharmonic beat can occur in a carrier-based PWM converter when the switching frequency is low and is an imperfect multiple of the grid frequency. Recognizing the beat as interaction of the switching sequence and switching frequency, mitigation techniques to reduce the beat and associated harmonics are investigated and verified through experiments. A simple displacement of switching frequency from the odd-triplen multiple of the grid frequency can effectively suppress the beat with an asynchronous PWM scheme.
引用
收藏
页码:1349 / 1359
页数:11
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