A nested finite element methodology (NFEM) for stress analysis of electronic products - Part II: Durability analysis of flip chip and chip scale interconnects

The nested finite element methodology (NFEM) presented in Part I of this series, is used in this paper to analyze the viscoplastic stress-state in a flip-chip-on-board (FCOB) and a chip scale package subjected to temperature cycling loads. The results are validated with conventional finite element method (CFEM). An energy-partitioning (EP) damage model is used to predict cycles to failure, based on the energy densities obtained from NFEM and CFEM, and results are compared with experiments.