Optimal memory organization for scalable texture codecs in MPEG-4

被引:45
作者
Lafruit, G [1 ]
Nachtergaele, L [1 ]
Bormans, J [1 ]
Engels, M [1 ]
Bolsens, I [1 ]
机构
[1] Inter Univ, Micro Elect Ctr, B-3001 Louvain, Belgium
关键词
still texture coding; VLSI architectures; zero-tree wavelet coding;
D O I
10.1109/76.752091
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper addresses the problem of minimizing memory size and memory accesses in multiresolution texture coding architectures for discrete cosine transform (DCT) and wavelet-based schemes used, for example, in virtual-world walkthroughs or facial animation scenes of an MPEG-4 system. The problem of minimizing the memory cost is important since memory accesses, memory bandwidth limitations, and in general the correct handling of the data hows have become the true critical issues in designing high-speed and low-power video-processing architectures and in efficiently using multimedia processors. For instance, the straightforward implementation of a multiresolution texture codec typically needs an extra memory buffer of the same size as the image to be encoded/decoded, We propose a new calculation schedule that reduces this buffer memory size with up to two orders of magnitude, while still ensuring a number of external (off-chip) memory accesses that is very close to the theoretical minimum. The analysis is generic and is therefore useful for both wavelet and multiresolution DCT codecs.
引用
收藏
页码:218 / 243
页数:26
相关论文
共 26 条
[1]  
[Anonymous], LIFTING SCHEME CUSTO
[2]   THE LAPLACIAN PYRAMID AS A COMPACT IMAGE CODE [J].
BURT, PJ ;
ADELSON, EH .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1983, 31 (04) :532-540
[3]  
CHAKRABARTI C, 1993, P VLSI SIGNAL PROCES, V6, P507
[4]  
DENK TC, 1994, P IEEE INT S CIRC SY, V3, P77
[5]  
GLIDDEN R, 1997, GRAPHICS PROGRAMMING, P48
[6]   Design of a low power video decompression chip set for portable applications [J].
Gordon, BM ;
Tsern, E ;
Meng, TH .
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1996, 13 (2-3) :125-142
[7]  
*ISO IEC, 1997, 144962 ISOIEC
[8]   VLSI ARCHITECTURE FOR THE DISCRETE WAVELET TRANSFORM [J].
KNOWLES, G .
ELECTRONICS LETTERS, 1990, 26 (15) :1184-1185
[9]  
Lafruit G., 1995, Applied Signal Processing, V2, P87
[10]  
LAFRUIT G, IN PRESS IEEE T VLSI