Utilizing surplus timing for power reduction

被引：43

作者：

Hamada, M ^{[1
]}

Ootaguro, Y ^{[1
]}

Kuroda, T ^{[1
]}

机构：

[1] Toshiba Corp, Syst LSI Res & Dev Ctr, Kawasaki, Kanagawa, Japan

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929730

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.

引用

页码：89 / 92

页数：4

共 3 条

[1] Low-power CMOS digital design with dual embedded adaptive power [J].

Kuroda, T ;

Hamada, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (04) :652-655

[2]

Nose K., 2000, Proceedings ASP-DAC 2000. Asia and South Pacific Design Automation Conference 2000 with EDA TechnoFair 2000. (Cat. No.00EX389), P469, DOI 10.1109/ASPDAC.2000.835145

[3] ALPHA-POWER LAW MOSFET MODEL AND ITS APPLICATIONS TO CMOS INVERTER DELAY AND OTHER FORMULAS [J].

SAKURAI, T ;

NEWTON, AR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (02) :584-594

← 1 →