Highly reliable W/TiN/pn-poly-Si gate CMOS technology with simultaneous gate and source/drain doping process

被引：16

作者：

Wakabayashi, H

Andoh, T

Sato, K

Yoshida, K

Miyamoto, H

Mogami, T

Kunio, T

机构：

来源：

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996 | 1996年

关键词：

D O I：

10.1109/IEDM.1996.553623

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel W/TiN/pn-poly-Si gate structure has been developed for merged memory and logic LSIs by using sub-quarter micron pn-poly-Si gate CMOS devices. Low-resistance and thermally stable tungsten (W) films were obtained by 5-nm titanium nitride (TiN) film between tungsten film and poly-Si film. This W/TiN/poly-Si gate electrode has a good heat resistance after RTA process at 1000 degrees C for 10 sec. 0.22-mu m W/TiN/pn-poly-Si gate CMOS devices without inter diffusion through the gate electrode were fabricated by using a simultaneous gate and source/drain (SD) doping process.

引用

页码：447 / 450

页数：4