Synchronous handshake circuits

We present the synchronous implementation of handshake circuits as an extra feature in the otherwise asynchronous design flow based on Tangram. This synchronous option can be used in the mapping onto FPGAs or as a fall-back option to provide a circuit that is easier to test and integrate in a synchronous environment. When single-rail and synchronous realizations of the same handshake circuit are compared the synchronous versions typically require fewer slate-holding elements, occupy less area, have similar performance, bur consume significantly more power (in the examples studied up to a factor four). Synchronous handshake circuits provide a means to study clock-gating techniques based on the synthesis starring from a behavioral-level specification. In addition, the study provides hints as to where the asynchronous handshake circuits may be optimized further.