Frequency granularity in digital phaselock loops

被引：27

作者：

Gardner, FM

机构：

[1] Gardner Research Company, Palo Alto

来源：

IEEE TRANSACTIONS ON COMMUNICATIONS | 1996年 / 44卷 / 06期

关键词：

D O I：

10.1109/26.506392

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 [电气工程]; 0809 [电子科学与技术];

摘要：

Frequency of a digital phaselock loop (DPLL) is necessarily quantized, Feedback around the quantizing nonlinearity leads to a steady-state limit cycle, Properties of the limit cycle were obtained by computer simulation, and are reported here, Empirical formulas for guidance in DPLL design were developed.

引用

页码：749 / 758

页数：10