Effect of extreme surface roughness on the electrical characteristics of ultra-thin gate oxides

被引:34
作者
Houssa, M [1 ]
Nigam, T [1 ]
Mertens, PW [1 ]
Heyns, MM [1 ]
机构
[1] IMEC, B-3001 Louvain, Belgium
关键词
D O I
10.1016/S0038-1101(98)00200-7
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The effect of extreme surface roughness on the electrical characteristics and gate oxide integrity of MOS (metaloxide-semiconductor) capacitors with ultra-thin SiO2 layers is reported. The Si surface roughness is increased by NH4OH dips prior to gate oxidation. The Si and SiO2 surfaces are then characterized by lightscattering Haze and AFM measurements. Electrical measurements are undertaken on MOS capacitors with a 6.4 and 4.2 nm gate oxide. Results are compared for wafers with RMS roughness of respectively 0.09 and 9 nm. It is shown that the tunneling current is increased in case of extreme Si surface roughness and does not follow the simple Fowler-Nordheim expression. Quantum oscillations in 4.2 nm oxides are also shown to be much damped by Si/SiO2 interface roughness. The effect of surface roughness on gate oxide reliability is investigated through charge-to-breakdown Q(BD) measurements performed at constant current and constant voltage stress. It is shown that intrinsic Q(BD) values determined by constant current stressing are higher for oxides on rough surfaces in case of substrate injection while the opposite trend is observed in case of gate injection. All results can be consistently explained by considering the effect of a distribution of oxide thicknesses on the gate oxide properties. (C) 1998 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:159 / 167
页数:9
相关论文
共 15 条
[1]   DETERMINATION OF TUNNELING PARAMETERS IN ULTRA-THIN OXIDE LAYER POLY-SI/SIO2/SI STRUCTURES [J].
DEPAS, M ;
VERMEIRE, B ;
MERTENS, PW ;
VANMEIRHAEGHE, RL ;
HEYNS, MM .
SOLID-STATE ELECTRONICS, 1995, 38 (08) :1465-1471
[2]   WEAR-OUT OF ULTRA-THIN GATE OXIDES DURING HIGH-FIELD ELECTRON-TUNNELING [J].
DEPAS, M ;
VERMEIRE, B ;
MARTENS, PW ;
MEURIS, M ;
HEYNS, MM .
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1995, 10 (06) :753-758
[3]  
DEPAS M, 1995, P 26 IEEE SEM INT SP
[4]   Dependence on gate work function of oxide charging, defect generation, and hole currents in metal-oxide-semiconductor structures [J].
DiMaria, DJ .
JOURNAL OF APPLIED PHYSICS, 1997, 81 (07) :3220-3226
[5]  
HAN LK, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P617, DOI 10.1109/IEDM.1994.383334
[6]   Effect of silicon substrate microroughness on gate oxide quality [J].
Hegde, RI ;
Chonko, MA ;
Tobin, PJ .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1996, 14 (05) :3299-3304
[7]   CHARACTERIZATION OF SILICON SURFACE MICROROUGHNESS AND TUNNELING TRANSPORT THROUGH ULTRATHIN GATE OXIDE [J].
HIROSE, M ;
HIROSHIMA, M ;
YASADA, T ;
MIYAZAKI, S .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A-VACUUM SURFACES AND FILMS, 1994, 12 (04) :1864-1868
[8]   MODELING AND CHARACTERIZATION OF GATE OXIDE RELIABILITY [J].
LEE, JC ;
CHEN, IC ;
HU, CM .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (12) :2268-2278
[9]  
MEURIS M, 1995, SOLID STATE TECH JUL, P109
[10]  
Moazzami R., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P710, DOI 10.1109/IEDM.1988.32911