Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and thin AIN) and TaN/HfO2 Gate stack

被引:88
作者
Whang, SJ [1 ]
Lee, SJ [1 ]
Gao, F [1 ]
Wu, N [1 ]
Zhu, CX [1 ]
Pan, JS [1 ]
Tang, LJ [1 ]
Kwong, DL [1 ]
机构
[1] Natl Univ Singapore, Silicon Nano Device Lab, Dept Elect & Comp Engn, Singapore 119260, Singapore
来源
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年
关键词
D O I
10.1109/IEDM.2004.1419140
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Ge-MOS devices (EOT similar to 7.5 Angstrom, Jg similar to 10(-3) A/cm(2)) are fabricated on both n- & p-type Ge-substrates, using novel surface passivation and TaN/HfO2 gate stack. Results show that the plasma-PH3 treatment and thin AlN layer at HfO2/Ge interface are effective to suppress the GeO formation, which is mainly formed during HfO2 deposition, and prevent Ge out-diffusion, resulting in improved C-V characteristics for n-MOS device with extremely low leakage. Thermal stability study of TaN/HfO2/Ge gate stack shows that low leakage with thin EOT can be obtained after postanneal at 500 degreesC and degradation is observed above 600 degreesC. It is also observed that good Ge n(+)-p and p(+)-n diode characteristics are achieved by S/D activation at 500 degreesC and 400degreesC, respectively. Both p- & n-MOSFETs are fabricated by conventional self aligned process with maximum temperature of 500 degreesC. Compared to reported SFMOSFETs, the mobility enhancement of 1.6X for hole and 1.8X for electron is observed with Ge-MOSFETs.
引用
收藏
页码:307 / 310
页数:4
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