p-n junction-based wafer flow process for stencil mask fabrication

The development of stencil masks is considered to be critical to the success of the new ion projection lithography technology. We present here a p-n junction wafer flow process where all fabrication steps are realized on a bulk Si wafer except the final trench etching through the 4-mu m-thick Si membrane. Stencil masks were produced in a conventional complementary metal-oxide-semiconductor 150 mm wafer line, using an e-beam direct writing tool for patterning. The resist patterns were transferred by standard reactive ion etching (RIE) into a stress-controlled SiON hard mask layer. Subsequent to depositing an Al metal layer for contact to the n-doped wafer surface, the membrane was realized by a wet chemical etch which implemented well established reverse biased p-n junction etch stop techniques. Then, openings through the Si membrane were etched by RIE or inductively coupled plasma etching. Finally, the remaining hard mask layer was removed in BHF. The realized Si membrane diameter was 120 mm with a stencil pattern field of 60 mm x 60 mm. Results from LMS-IPRO placement measurements are in agreement with the simulation of the stencil mask fabrication process using finite element methods. (C) 1998 American Vacuum Society. [S0734-211X(98)03506-9].