High-density 8Mb 1T-1C ferroelectric random access memory embedded within a low-power 130nm logic process

被引：17

作者：

Summmerfelt, S. R. ^{[1
]}

Moise, T. S. ^{[1
]}

Udayakumar, K. R. ^{[1
]}

Boku, K. ^{[1
]}

Remack, K. ^{[1
]}

Rodriguez, J. ^{[1
]}

Gertas, J. ^{[1
]}

McAdams, H. ^{[1
]}

Madan, S. ^{[1
]}

Eliason, J. ^{[2
]}

Groat, J. ^{[2
]}

Kim, D. ^{[2
]}

Staubs, P. ^{[2
]}

Depner, M. ^{[2
]}

Bailey, R. ^{[2
]}

机构：

[1] Si Technol Dev Texas Instruments Inc, Dallas, TX 75266 USA

[2] Ramtron Int Corp, Colorado Springs, CO USA

来源：

2007 SIXTEENTH IEEE INTERNATIONAL SYMPOSIUM ON THE APPLICATIONS OF FERROELECTRICS, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/ISAF.2007.4393151

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O-3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra- low-power devices.

引用

页码：9 / +

页数：2

共 4 条

[1]

Eliason J, 2005, IEEE CUST INTEGR CIR, P427

[2]

KIM JH, 2006, IEDM

[3]

Moise TS, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P535, DOI 10.1109/IEDM.2002.1175897

[4] Bit distribution and reliability of high density 1.5 V ferroelectric random access memory embedded with 130 nm, 5 Im copper complementary metal oxide semiconductor logic [J].

Udayakumar, K. R. ;

Boku, K. ;

Remack, K. A. ;

Rodriguez, J. ;

Summerfelt, S. R. ;

Celii, F. G. ;

Aggarwal, S. ;

Martin, J. S. ;

Hall, L. ;

Matz, L. ;

Rathsack, B. ;

McAdams, H. ;

Moise, T. S. .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B) :3202-3206

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