Simulation of test wafer consumption in a semiconductor facility

被引：9

作者：

Foster, B ^{[1
]}

Meyersdorf, D ^{[1
]}

Padillo, JM ^{[1
]}

Brenner, R ^{[1
]}

机构：

[1] TEFEN Ltd, Foster City, CA 94404 USA

来源：

ASMC 98 PROCEEDINGS - 1998 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: THEME - SEMICONDUCTOR MANUFACTURING: MEETING THE CHALLENGES OF THE GLOBAL MARKETPLACE | 1998年

关键词：

D O I：

10.1109/ASMC.1998.731576

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A discrete event simulation methodology was developed to assist in managing test wafer usage in semiconductor fabs. The purpose of modeling test wafer usage is to predict the number of new test wafers required, test wafer WIP levels, and how to downgrade test wafers to reduce costs of purchasing new test wafers. The test wafer simulation methodology is a detailed yet accurate way to predict test wafer consumption. The methodology has been implemented in a 200mm development facility resulting in considerable cost savings by reducing the overall WIP levels of test wafers.

引用

页码：298 / 302

页数：5