A 64Mbit embedded FeRAM utilizing a 130nm, 5LM Cu/FSG logic process

被引:14
作者
McAdams, H [1 ]
Acklin, R [1 ]
Blake, T [1 ]
Fong, J [1 ]
Liu, D [1 ]
Madan, S [1 ]
Moise, T [1 ]
Natarajan, S [1 ]
Qian, N [1 ]
Qui, Y [1 ]
Roscher, J [1 ]
Seshadri, A [1 ]
Summerfelt, S [1 ]
Du, X [1 ]
Eliason, J [1 ]
Kraus, W [1 ]
Lanham, R [1 ]
Li, F [1 ]
Pietrzyk, C [1 ]
Rickes, J [1 ]
机构
[1] Texas Instruments Inc, Dallas, TX 75243 USA
来源
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年
关键词
FRAM; eFRAM; ferroelectric; 1T1C;
D O I
10.1109/VLSIC.2003.1221194
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A low-voltage (1.3V), 64Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30ns while consuming 0.57mW/MHz at 1.37V. An eFRAM density of 1.13 Mb/mm(2) is achieved with a cell size of 0.54um(2) and capacitor size of 0.25um(2).
引用
收藏
页码:175 / 176
页数:2
相关论文
共 4 条
[1]  
Moise T. S., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P940, DOI 10.1109/IEDM.1999.824305
[2]  
Moise TS, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P535, DOI 10.1109/IEDM.2002.1175897
[3]  
Rickes JT, 2002, INTEGR FERROELECTR, V48, P109, DOI [10.1080/10584580290171522, 10.1080/10584590290171522]
[4]   Demonstration of scaled (≥0.12 μm2) Pb(Zr,Ti)O3 capacitors on W plugs with Al interconnect [J].
Summerfelt, SR ;
Moise, TS ;
Xing, G ;
Colombo, L ;
Sakoda, T ;
Gilbert, SR ;
Loke, ALS ;
Ma, S ;
Wills, LA ;
Kavari, R ;
Hsu, T ;
Amano, J ;
Johnson, ST ;
Vestcyk, DJ ;
Russell, MW ;
Bilodeau, SM ;
van Buskirk, P .
APPLIED PHYSICS LETTERS, 2001, 79 (24) :4004-4006