A new procedure to define the zero-field condition and to delineate pn-junctions in silicon devices by Scanning Capacitance Microscopy

被引：4

作者：

Stangoni, M ^{[1
]}

Ciappa, M ^{[1
]}

Fichtner, W ^{[1
]}

机构：

[1] ETH, Integrated Syst Lab, Swiss Fed Inst Technol, CH-8092 Zurich, Switzerland

来源：

MICROELECTRONICS RELIABILITY | 2003年 / 43卷 / 9-11期

关键词：

D O I：

10.1016/S0026-2714(03)00293-2

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Basing on theoretical considerations and on physical simulations, a new procedure is proposed to define the location of the electrical junction in pn-junctions by Scanning Capacitance Microscopy and to extract at the same time the related zero-field condition. Applications of this procedure are shown in the case of epitaxial and shallow junctions. (C) 2003 Elsevier Ltd. All rights reserved.

引用

页码：1651 / 1656

页数：6

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