Design and implementation of a 1024-point pipeline FFT processor

被引：148

作者：

He, S ^{[1
]}

Torkelson, M ^{[1
]}

机构：

[1] Univ Lund, Dept Appl Elect, S-22100 Lund, Sweden

来源：

IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/CICC.1998.694922

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-2(2) algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 mu CMOS technology and takes an area of 40 mm(2). With 3.3v power supply, it can compute 2(n), n = 0, 1,..., 10 complex point forward and inverse FFT in real time with up to 30MHz sampling frequency. The SQNR is above 50dB for white noise input.

引用

页码：131 / 134

页数：4