Pixel detector readout electronics with two-level discriminator

In preparation for a silicon pixel detector with more than 3000 readout channels per chip for operation at the future large hadron collider (LHC) at CERN the analog frontend of the readout electronics has been designed and measured on several test-arrays with 16 by 4 cells. They are implemented in the HP 0.8 mu m process but compatible with the design rules of the radiation hard Honeywell 0.8 mu m bulk process. Each call contains bump bonding pad, preamplifier, discriminator and control logic for masking and testing within a layout area of only 50 mu m by 140 mu m. A new two-level discriminator scheme has been implemented to cope with the problems of time-walk and interpixel cross-coupling. The measured gain of the preamplifier is 900mV for a minimum ionizing particle (MIP, about 24000 e(-) for a 300 mu m thick Si-detector) with a return to baseline within 750ns for a 1MIP input signal. The full readout chain (without detector) shows an equivalent noise charge of 60e(-) r.m.s. The time-walk, a function of the separation between the two threshold levels, is measured to be 22ns at a separation of 1500e(-), which is adequate for the 40MHz beam-crossing frequency at the LHC. The interpixel cross-coupling, measured with a 40fF coupling capacitance, is less than 3%. A single cell consumes 35 mu W at 3.5V supply voltage.