Charge trapping in aggressively scaled metal gate/high-κ stacks

被引：22

作者：

Gusev, EP ^{[1
]}

Narayanan, V ^{[1
]}

Zafar, S ^{[1
]}

Cabral, C ^{[1
]}

Cartier, E ^{[1
]}

Bojarczuk, N ^{[1
]}

Callegari, A ^{[1
]}

Carruthers, R ^{[1
]}

Chudzik, M ^{[1
]}

D'Emic, C ^{[1
]}

Duch, E ^{[1
]}

Jamison, P ^{[1
]}

Kozlowski, P ^{[1
]}

LaTulipe, D ^{[1
]}

Maitra, K ^{[1
]}

McFeely, FR ^{[1
]}

Newbury, J ^{[1
]}

Paruchuri, V ^{[1
]}

Steen, M ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, SRDC, Yorktown Hts, NY 10598 USA

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419274

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A comparative analysis of charge trapping in advanced metal gate/high-kappa stacks with EOT below 1 nm (corresponding to CETs, or T-inv in the 1.2 - 1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates), (ii) high-kappa dielectric material (HfO2, HfO2:N, HfSiO, HfSiON, ZrO2, Al2O3): (iii) high-kappa deposition technique (MOCVD vs. ALD), (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-kappa layer and poly-Si plays a major role in charge trapping degradation.

引用

页码：729 / 732

页数：4

共 7 条

[1]

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[2]

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[7]

*ZAFAR S, 2002, IEDM, P517

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