Interconnect capacitance, crosstalk, and signal delay for 0.35 mu m CMOS technology

With the advent of deep-submicron technologies and sub-nano second switching circuits, VLSI interconnects become one of the important limiting factors of today's high-speed and high-density circuit performances, which arises with signal dispersion, crosstalk, and unmatched signal timing. To overcome signal integrity problems, the accurate prediction of the electrical characteristics of interconnects is essential. This paper presents interconnect line characterization, modeling, and simulation of 0.35 mu m CMOS logic technology. The final goal of this work is aimed at building the database of electrical parameters of multi-layered interconnects and providing new guidelines to obtain optimal interconnect design for high-speed and high-density VLSI circuits.