An optical centralized shared-bus architecture demonstrator for microprocessor-to-memory interconnects

An architecture demonstrator of an innovative interconnect scheme called the optical centralized shared-bus is presented in this paper. This architecture retains the advantages of shared-bus topology while at the same time specifying a uniform interface between the electrical and the optical backplane layers in contrast to other proposed architectures. For the first time, a fanout equalized optical backplane bus is demonstrated. In this architecture demonstrator, the data paths required for the microprocessor-to-mernory interconnects are provided by the optical centralized shared-bus. The optoelectronic interface modules are optimized to support data rates up to 1.25 Gb/s. The objective of this microprocessor-to-memory interconnects demonstration is to ensure the feasibility of applying this innovative architecture in real systems.