Optically interconnected integrated circuits to solve the CMOS interconnect bottleneck

被引:16
作者
Dhoedt, B [1 ]
Baets, R [1 ]
Van Daele, P [1 ]
Heremans, P [1 ]
Van Campenhout, J [1 ]
Hall, J [1 ]
Michalzik, R [1 ]
Schmid, A [1 ]
Thienpont, H [1 ]
Vounckx, R [1 ]
Neyer, A [1 ]
O'Brien, DC [1 ]
Van Koetsem, J [1 ]
机构
[1] Univ Ghent, IMEC, Dept Informat Technol INTEC, B-9000 Ghent, Belgium
来源
48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS | 1998年
关键词
D O I
10.1109/ECTC.1998.678831
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The performance of future generation data processing systems will be set by interconnect limitations rather than by IC performance. The main reason for this expected I/O-bottleneck is the projected increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion, EMI) will lead to bandwidth limitations, in turn resulting in a mismatch between silicon processing capabilities and interconnect performance. Optical I/O over the entire chip area is pursued as a solution to these interconnection problems in the European Community funded ESPRIT project OIIC ("OpticalIy Interconnected Integrated Circuits"). In this approach, data transfer from the whole chip area is facilitated through two dimensional arrays (array pitch : 250 mu m) of optical channels, consisting of opto-electronic components flip-chip mounted on CMOS circuitry and aligned to passive optical pathways. Data rate objectives are 0.5 - 1 Gb/s per channel. As a principal choice in this project, a 2D array of small diameter (125 mu m) Plastic Optical Fibres is used as a flexible transmission medium. The large numerical aperture of this fibre (typically NA=0.5) and its flexibility allow for compact assembly (and hence low head room modules) and relatively coarse alignment.
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页码:992 / 998
页数:7
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