A radix-8 CMOS S/390 multiplier

The multiplier of a S/390 CMOS microprocessor is described. It is implemented in an aggressive static CMOS technology with 0.20 mu m effective channel length. The multiplier has been demonstrated in a single-image shared-memory multiprocessor at frequencies up to 400 MHz. The multiplier requires three machine cycles for a total latency of 7.5 ns. Though, the design can support a latency of 4.0 ns if the latches are removed. The design goal was to implement a versatile S/390 multiplier with reasonable performance at a very aggressive cycle time. The multiplier implements a radix-8 Booth algorithm and is capable of supporting S/390 floating-point and fixed-point multiplications and also division and square root. Logic design and physical design issues are discussed relating to the Booth decode and counter tree implementations.